Nanoarchitectonics based on Memristive Nanowire Networks

Transistor-based architectures in the traditional von Neumann architecture are reaching their limit exhibiting a wide gap in performances comparing the CPU and the memory addressing, where the latter represents a big constraint in operational frequency. New computing paradigms are necessary to overcome these limitations, where bio-mimetic approaches come to help: brain-inspired paradigms suggest to perform storage and processing operations in a spatial and physical correlated frame- work. One of the devices which lets this approach possible is a novel analog device: the memristor. Acting as an artificial synapse, this component exhibits resistive switching and memory properties, which allow the mimicking of brain plasticity. Arranged in different architectures they can be involved in the building up of new computing paradigms, such as reservoir computing. This approach basically refers to the mapping of an input on a higher dimensional space dynamical system (reservoir) to emphasize and extrapolate spatio-temporal input correlations, which are classified by a simple readout function (usually, a one-layer neural network). This work deals with self-organizing memristive nanowire networks, which show high connectivity and the capability to replicate some of the characteristics of biological neural networks: homo- and hetero-synaptic plasticity, paired pulse facilitation and short-term plasticity. After discussing the fabrication and experimental measure- ments, the compact model discussed in the framework of this thesis is exploited to extrapolate phenomenological behavior of network internal state and a quantitative analysis by fitting experimental curves. Model replication of experimental homo- and hetero-synaptic data is demonstrated, both in a qualitative and quantitative point of view up to a certain discussed degree of confidence. By using this model, it was evaluated the possibility to perform reservoir computing on these kind of devices is investigated through a simulation approach, exploiting the nanowire network as a reservoir and a one-layer neural network as a readout function. Written digit recognition task is demonstrated and optimized by considering different degrees of freedom of the implemented process, such as electrodes configuration, input processing, managing of reference voltages. Such developed system implements simultaneously, however, memristive and CMOS technology. In order to exploit energy and speed advantages of memristive technology over the traditional one, the possibility to build up a fully-memristive system is demonstrated, again, through simulations of real hardware components: the memristive crossbar array. Also, a discussion on the energy consumption of the above described architecture is pro- vided. This work serves as a demonstration of one possible computing approach exploiting self-organizing memristive nanowires network devices, which have been modeled in their relevant behaviors. As a future perspective, models developed in the frame- work of this thesis can support and complement experimental activity towards the implementation of new computing paradigms in self-organized NW networks.