Design and optimization of Computational SRAM architectures dedicated to highly data-centric applications

??I have undergone my Master Thesis at CEA Grenoble working on an emerging compu-ting architecture called Computational-SRAM (C-SRAM) based on SRAM memory technol-ogy which allows to perform calculations directly in memory without going through a proces-sor. These novel architectures are meant to be the most energy efficient possible to satisfy the needs of targeted data-centric and artificiel intelligence applications. ??In fact, an initial C-SRAM controller was already implemented by my team at CEA Grenoble. The aim of this internship was to optimize this controller by implementing new computing functionalities as well as reducing its energy consumption and its surface. The same work could be also be adapted to different types of memories. ??First, I had to familiarize with the existing design flow already developed by the la-boratory. I spent much time trying to locate possible optimization points for the design under study. Therefore, I had the chance to interviene at each step of this flow, from the RTL mod-elling (in Sytem Verliog) through the synthesis (using Design Compiler) and until the physical implementation (using Cadence Innovus) and the verification step (using Primetime PX). ??It is fair to say that all the work we conducted on the initial design of C-SRAM led to several interesting results that could be hugely valuable for choosing the best design options and reach optimum energetic points as aimed in the beginning of this internship. Hence, we can summarize them in the upcoming points: ❖??Adding new functionalities to the C-SRAM instructions set (shifts and HSWAP). ❖??Implementing a 5-stage pipeline in the RTL model helped us reach better power, per-formance and area (PPA) tradeoffs. We were able to increase the operating clock frequency while maintaining a proper function of the system. In addition to that, we gained 31% in total chip area and 42% in power at a frequency of 500MHz. ❖??We completed a detailed power analysis of C-SRAM that gave us an idea on the par-ticipation of each power attribute in the total consumption. We did characterize also the ener-getic cost of different C-SRAM operations and even of every pipeline stage executed. ❖??We determined that it is better to use the largest memory size available instead of as-sembling smaller macros together to reach the same size capacity. However, this second option was really useful to reach memory capacities beyond what we had at our disposition. ❖??Increasing the clock frequency is rewarding when it comes to reducing the energy cost of C-SRAM operations. This could be extremely favorable for future integration of C-SRAM. Yet, it generated more timing violations and power consumed which should be also analyzed carefully. ❖??We managed to successfully implement a C-SRAM design with several memory in-stances assembled together to reach high size capacities (128kB). This represented a chip ver-sion that could be sufficient for targeted applications (neural networks for example) to per-form their computations efficiently. ?? ??Thus, the study realized on the impact of various factors on C-SRAM performances revealed to be very helpful in the pursuit of optimum energetic points. Nevertheless, there were other possible optimizations which could be implemented later. Overall, the results obtained through this work demonstrated that C-SRAM-like emerging architectures may represent an efficient solution for the huge amount of power consumed by data-centric applications.