Study and development of a real-time monitoring system for parametric experimental testbed

The objective of this thesis is to develop a real-time monitoring system for parametric testbed and analyze its behavior depending on the frequency of the system. A testbed is a platform used for testing particular modules. This system is composed by two different parts: the first one is a monitoring subsystem, which is an interface that extracts the raw data and gathers it in order to analyze it and also provides the test with the inputs. The second part is the experimental subsystem, which is the collection of modules or prototypes to be experimented with. For this thesis, the first part has the condition of being a real-time monitoring system, which means that has to be continuously updating the information of the test that is being carried out. Other condition of the project is that each subsystem of the testbed must be developed in a different FPGA, which means that two boards are used, the monitor and the Device Under Test (DUT). The election of the FPGAs is not a critical aspect of this thesis, and for the sake of simplicity it has been decided to use the same model of FPGA for both subsystems, although this is not necessary and different boards could be used as well. The FPGA used is a PYNQ-Z2, which is based on Xilinz Zynq SoC. As it has been said, the monitoring subsystem is the interface that feeds the inputs to the experimental part and also the one that collects the outputs and analyzes them. For this, both boards must be connected by wires that are connected to the Raspberry pins of the FPGA. It is easy to deduce that the number of signals that can be exchanged at each moment is limited by the number of pins available, and for this project it has been set to eight input and eight output pins. In addition to this sixteen signals, another five have been added, that correspond to the general reset and enables used in the process of sending and receiving information, giving a total of twenty-one wires. This limitation of pins leads to the main issue of the thesis, developing a communication system that may allow sending more inputs/outputs than the available number. This task has been overcome by developing VHDL modules implemented in the DUT board. In the scenario of receiving the inputs by this board, the information is sent by the monitor in packages of eight bits, and this module gathers all the packages into one signal that is sent to the test. For the opposite case, in which the DUT sends the information to the monitor, it is this first board the one that splits the data in packages of eight bits and sends them to the other subsystem. This communication is carried out by using two handshaking signals (the four enables mentioned before), the first warns the receiving module that the information is being sent, and the other that states whether or not the system that receives the data is ready to get new information. In order to test the correct behavior of the communication modules, a shift register has been used as a Unit Under Test (UUT) in the DUT. The project has been designed in VIVADO and SDK. The inputs and outputs of the test are stored in an AXI BRAM in the monitor board, and for this reason, it is necessary to connect the PL (Programmable logic) to the PS (Processing System), and using AXI GPIOs, the information can flow from one to another. Once the system is working, the clock frequency of the boards has been changed in order to find the value in which the system is not able to work properly anymore.