METHODOLOGIES FOR SOC VERIFICATION

Nowadays, with he increase of the complexity of system on chips SOC, the ASIC industry struggles to meet schedules of time to market TTM. System on chips market is complex in term of the business and technology point of view. However, the time to market enforces a huge pressure to this industry. As a consequence of these factors: appearance of new challenges, among them the top one which is verification. This last one consumes more than 70 percent of design effort. In 1999,Vertual Socket Alliance (VSIA) held a workshop, with the aim of discussing the verification challenges for the new ASIC architecture, the conclusion of this workshop that gathered only the experts of verification in the world was verification is hard. After a length and extensive discussion the final decision was verification is not hard, it is very hard. Accompanied to this conclusion,they have observed that no single design tool was able to solve the problem. However, by using a complex sequence of techniques and tools, the number of design errors will be reduced at least to minimum. Example of The techniques used: directed and random verification, formal techniques and don’t forget classical simulation. The third meeting of VSIA completed with verification is not just hard,it is very, very hard ! Verifying the correctness of the final design is the key to design more and more complex SOCs and exploiting leading_edge process technologies. The better to discover the hidden bugs in earlier stages the better in term of the cost,companies often end up with costly mistake. Hence, it is important for the companies to select the suitable tool and techniques for verification. One of the modern and effective methodologies is universal verification methodology UVM. in the next chapters ,it is described the verification tools used to verify a SOC and explaining how much UVM is efficient and how to use its language.