Development of an FPGA-based Architecture for the Analysis of a High-Speed Serial Link Protocol

The thesis aims for the development of a configurable and extensible hardware architecture to monitor a proprietary protocol, called Sakura, for high-speed communication links. The project issued from the need of an item capable of capturing and analyzing the data traffic exchanged in a specific modular test infrastructure developed by Advantest Corporation. The involved parts are connected through optical links and their communication is built upon the 40GBASE-SR Ethernet standard. The system is thus founded on the adoption of high-speed technologies able to support the transmission of large quantities of data at high data rates. In such infrastructures, exploiting the existing communication modules to have access to the exchanged information at different levels of protocol abstraction might be unfeasible, due to the large resources and heavy workload required. Therefore, the designed system must be detached from the communication endpoints and provide the means to monitor the custom protocol from the lowest possible layer, retrieving the data needed to analyze any higher abstraction layer. The first goal of this work consisted in evaluating different hardware structures suited for the implementation of the required capturing tasks. The selection process led to the choice of a Field-Programmable Gate Array (FPGA) board equipped with QSFP+ transceiver interfaces. The transceiver functionalities embedded in the Intel Arria 10 FPGA device were used to support the full-duplex communication with the involved modules. Following the choice of the equipment, the treatment of the captured data within the FPGA programmable logic was analyzed, preparing for the implementation phase. The protocol analyzer was designed to work as a man-in-the-middle system, where the data traffic is received and retransmitted in both directions with a throughput of 82.5 Gbps, while being decoded and captured according to three different user modes. ?? The resulting design employs only 5% of the total adaptive logic modules (AMLs) and 77% of the RAM memory blocks of the FPGA, making it possible to extend the existing functionalities and to be integrated with a PCIexpress FPGA-to-Host interface. The modules composing the design were simulated through specifically designed testbench environments. The hardware testing phase successfully proves the ability of the system to receive data from both the communication directions and correctly decode them. A communication fault has arisen in the transmitting chains, preventing the testing phase to be completed. The flawed behaviour of the system was analyzed and discussed in order to ease the future debugging activity. The conclusion of the harware testing phase is left as future development of this thesis project.