Study of Verification Techniques for Digital Architectures

Nowadays digital systems are continuously growing in complexity and the ASIC industry is struggling to meet schedule. About two thirds of the industry are behind with their planned projects. Similarly, the industry is struggling to keep pace in terms of quality. In accordance with the studies reported in the literature, it can be noticed that there is a gap between the ability to fabricate and manufacture according to Moore’s law and what can actually be designed in reality within a given project schedule. The first study was carried out by ITRS and refers to the productivity gap. The other one is a Collett study that describes functional verification and adoption of technology and again makes reference to the gap between what can be verified and what can be designed. A lot of organizations used to struggle to adopt advanced techniques: they were still using 1990 best practices in terms of directed tests and code coverage, implying that the industry has not necessarily kept up with verification techniques. It is clear that the ability to verify would improve significantly if organizations adopted more advanced verification techniques, instead of relying on older techniques that were state of the art in the early 1990s. Today roughly 40% of the industry has adopted functional coverage and roughly 40-41% of the industry has adopted constrained random. Assertions, which enable formal verification and go after these concurrent problems, have been adopted by roughly 37% of the industry. Such data show that the industry has failed to move forward in terms of advanced functional verification. Considering the importance of verification of digital architecture and the fact that in industry this takes up to 60% of time resources in a design project, this thesis is concerned with studying advanced techniques and methodologies for the verification of digital systems. The main objective is to apply the Universal Verification Methodology (UVM), now considered to be the standard approach to this matter, on both simple and complex integrated circuits. UVM is based on SystemVerilog and nowadays, it has become the first methodology adopted in the industry because it is adaptable and reusable, due to the fact that the code for a project can be used for a similar one with proper modifications, thus resulting in a significant saving in terms of resources. The terms “verification with SystemVerilog” and “verification with the UVM” are broadly synonymous. Indeed, the UVM is becoming so pervasive in verification practice that tool vendors are already beginning to offer precompiled versions of the UVM’s BCL (base class libraries), and built-in UVM-specific debug capability, as integral parts of their SystemVerilog simulation tools. It seems natural, then, to ask whether the facilities provided by the UVM should perhaps be integrated into the SystemVerilog core language and its IEEE-standardized language reference manual (LRM). SystemVerilog already has a range of verification specific constructs – in particular, temporal assertions, coverage, and constrained random generation. It is clear that the combination of SystemVerilog and the UVM provides users with a powerful toolkit that can be applied effectively to a wide range of problems in the domain of functional verification of digital hardware designs, increasing significantly the efficiency in the verification stage of a design project.