Hardware-Aware Dataflow Exploration and Mapping of Convolutional Neural Networks

State-of-the art Convolutional Neural Networks (CNNs) can perform tasks such as image classification or voice recognition with high precision, at the expense of high computational complexity and energy requirements. Making a design focused only on a single aspect could result in a system which is unable to satisfy energy or latency requirements, critical in several applications such as autonomous driving. This emphasizes the need for taking both the hardware specific requirements into consideration for a given application scenario. For highly-parallel processor architectures, this work provides two methods of design space exploration in the context of task-to-processor mapping, aiming to find the optimal resource binding strategy for a given network and hardware architecture, in a reasonable time. The first method is applied to two different algorithms, which are strided convolution and General Matrix Multiplication (GEMM). A detailed analysis of the first algorithm was carried out, which included the most common dataflows (DFs) with the addition of two new ones. For GEMM based convolution, three possible dataflows were formalized and implemented, which have not been described in literature to the best of our knowledge. Both the algorithms are mapped for a target energy, latency or a trade-off by analyzing the dataflows. The second method, which was only applied to strided convolution, explores the configurations of all loops to consider each possible DF, thereby covering a larger solution space. Following validation against state-of-the-art frameworks, the tool was used for design space exploration by changing the hardware configurations, algorithms and dataflows.