In digital design process, due to the large dimensions of the designs, automated techniques are needed for a fast design phase. Because of high complexity of the logic this circuits, verify that the implementation of the digital designer is correct and follows all the specfication defined by standard protocols, an automated process is needed as well for verification side. It's unfeasible for the verification engineer to develop a simple testbench by having an instance of the DUT (Design Under Test), sending stimulus to it, getting its outputs and checking and analizing that the DUT works properly. Somenthing more automated isneeded to verify fastly what the designer developed.