Universal Verification Methodology-based Testbench(UVM): The Verification Standard for digital design

In digital design process, due to the large dimensions of the designs, automated techniques are needed for a fast design phase. Because of high complexity of the logic this circuits, verify that the implementation of the digital designer is correct and follows all the specfication defined by standard protocols, an automated process is needed as well for verification side. It's unfeasible for the verification engineer to develop a simple testbench by having an instance of the DUT (Design Under Test), sending stimulus to it, getting its outputs and checking and analizing that the DUT works properly. Somenthing more automated is needed to verify fastly what the designer developed. The Universal Verification Methodology (UVM) aims to provide to verification engineer a layered structure, where each layer has a particular meaning for the final purpose of verifing the DUT. The idea of having a hierarchy in this structure is helpful for the verification engineer, so that it's possible to divide the problem in several steps and to not dealing with an huge verification scenario. To simplify, it's possible to distinguish between "data item" creation, "data driving" on DUT and "data checking" from DUT. An important help that we get from UVM is that its strcture is based on software classes. Being based on System Verilog (an Object Oriented Programming Language), it's possible to exploit the Inheritance, such that it's possible to extend classes from others, getting useful properties from parent classes and adding new features to child classes. Thanks to the software properties is more easy to verify huge hardware structures. Designing and verifying hardware are two phases that have to go in pararell to provide a good final result (HDL code) to the following steps of SoC's development.