Inspection, merging and re-architecture of a highly configurable debug IP subsystem.

Giuseppe Bonfrate, "Inspection, merging and re-architecture of a highly configurable debug IP subsystem" Master's Thesis Politecnico di Torino, 2019. The present work relies on two main topics: highly configurable IP cores and real-time debugging design for complex SoC architectures. Both of them can be thought as consequences of the growing complexity of silicon industry available platforms, representing at the same time a solution to simplify work flow and reliability of the final products. A functional RTL level merging of two debugging IP cores is performed by using a strongly parametrized approach to let a single design be configured to deploy different features depending on the environment in which it is instantiated. The full suite of checks performed over the design is detailed and the critical aspects of the process are discussed, then the result of the merging is tested with UVM testbenches in order to verify the correct behaviour of the final IP core.