Novel Sensor Processing Architecture for next Generation GNSS Receivers

GNSS receivers synchronize a local replica PRN Code relative to the tracked satellite with the received signal, which allows to estimate the distance traveled by the incoming signal. Tracking loops are used in a closed loop to track the code and carrier of the satellite signal. The current architecture of GNSS receivers for space applications like the AGGA4 are based on a system on chip in which a processor handles the carrier and code loop. These have a high computational burden and thus limit the number of tracked satellites as processors for space applications have a low clock frequency. With the upcoming new constellations like Galileo the number of visible GNSS satellites will increase, and a higher performance of the receiver will be necessary.\\ This thesis will analyze the current hardware-software partitioning of the receiver and improve its performance by adding additional hardware accelerators. To do this, different options to perform calculations in hardware are discussed and implemented on FPGA. As the accuracy of the receiver depends on this loops all modifications in the system will be compared to the initial processor based version to verify that no accuracy degradation is introduced while converting the tracking algorithm in fixed point.