Hardware Accelerators for Long short-term memory Neural Networks using High Level Synthesis (HLS)

Long short-term memory networks, referred as LSTMs, are a notable kind of recurrent neural networks. They allow you to overcome vanishing gradient problem. Some of the different applications of LSTM include speech recognition, handwriting generation and recognition, music generation and composition, etc. FPGA-based hardware accelerators have been used recently due to their good performance in terms of power and flexibility. In this thesis, hardware accelerators have been implemented, synthesized and optimized for LSTM with different data type and this is made possible by using Xilinx Vivado tool. The data types used are fixed point - 16, float and double. One of the bottlenecks faced during the synthesis is sigmoid activation function which is non-linear. A piecewise linear approximation is used for sigmoid function to overcome this issue. Different optimizations and directives are applied to explore different solution. Pragmas like loop pipelining and unrolling, array partitioning etc. are applied during the synthesis process to find the optimum solution. Co-simulation is performed to check the functionality and validity of generated RTL. The generated RTL is available in Verilog, VHDL and SystemC. The synthesized module can be export as an Intellectual Property (IP) and used in other Xilinx tools. It is possible to generate generic RTL which can be used for FPGA from other market vendors.