Hardware Architecture for Homomorphic Encrypted Spiking Neural Networks

This thesis proposes a parallelized, generalized architecture for SNN inference under privacy-preserving constraints. Input images start in plaintext, then are quantized and encrypted using the BFV homomorphic encryption scheme allowing computation to proceed on protected data. The pipeline consists of linear stages coordinated by a handshake FSM: start/valid/ready/done. Since homomorphic encryption does not support non linear operations, we decrypt downstream of the linear stack to perform Activation_LIF. This step aims to restore noise budget and may re-encrypt to continue processing where necessary. Noise Budget blocks at encryption and after each operation (e.g., convolution, pooling, linear layer) provide essential telemetry for parameter selection and failure diagnosis. The architecture is informed by software: we inherit the algorithmic decomposition and assess patterns from an existing software implementation. Moreover, the architecture represents a parallel design prioritizing speed over area. Kernel and weight values are ported from that software, trained on 60,000 images, and tested with a batch size of 256, achieving approximately 99% accuracy on MNIST and ≈90% on Fashion-MNIST in software; these serve as a reference (oracle) for verification and calibration of the hardware. Our evaluation focuses on functional equivalence to the software oracle, noise-budget profiles, and implementation metrics such as latency, throughput, and resource usage. We do not claim superiority over the software baseline; rather, we aim to assess feasibility and characterize the trade-offs inherent in staged decryptions for nonlinearities within a privacy-preserving SNN pipeline.