Gabriele Attanasio
Architectural coverage for FEAT_GCS in an AArch64 CPU.
Rel. Guido Masera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2025
Abstract
This thesis addresses the critical need for robust validation of emerging architectural features, with a particular focus on the Guarded Control Stack (GCS) introduced in the Arm Architecture 64-bit (AArch64). GCS is a key security enhancement aimed at strengthening Control-Flow Integrity (CFI) by using hardware-based mechanisms to prevent control-flow hijacking attacks. As modern processors grow increasingly complex, and the consequences of security flaws become more severe, there is a pressing need for validation methodologies that are both thorough and strictly aligned with architectural specifications. To address this challenge, the thesis presents a coverage-driven validation methodology specifically tailored to GCS. The main contribution of this work is the creation and integration of a dedicated sequence into an existing architectural coverage model, targeting the Guarded Control Stack feature.
This sequence was designed to systematically exercise all relevant architectural scenarios, including stack operations, entry and exit transitions, and exception handling interactions
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