Architectural Analysis and Performance Optimization of an I2C-to-AHB Bridge for RISCV DMA

In a system, data exchange between two elements, each operating within its own clock domain, may present certain critical issues when one of the elements is busy executing another task or works at a lower frequency, thereby becoming unable to properly participate in the transmission of information. An example of this system, which is also the focus of this thesis, is composed of a Power Management Integrated Circuit (PMIC) and an external Application Processor (AP). PMIC, via a RISCV, monitors and manages the battery status of the device in which is integrated. This data is stored in internal RAM (which has an AHB interface), and the AP, through the I2C interface, can exchange this information by performing read and write operations. However, the RAM can also be accessed by other components within the PMIC. If the AP initiates an operation while the AHB bus is already occupied, the corresponding transaction will be stalled, resulting in its failure. The focus of this thesis is: to study elements of the system involved in data transmission, to identify the corner cases that define the operating conditions under which the system works correctly, to determine the key factors leading to transmission failure when the system crosses these corners, and finally to develop an optimization aimed at reducing or removing such criticalities, thereby extending the range of optimal conditions and enhancing the overall robustness of the system. Following an analysis of operation statistics based on the specific application, it was decided to proceed with optimizing write operations. Read operations are left unchanged and may be subject to future optimization. The implemented solution consists of introducing a block that functions as a Repeater. In other words, it acts as a FIFO buffer which, in the event that access to the RAM is blocked (due to the reasons previously mentioned), temporarily stores the data intended for RAM memory. As soon as the AHB bus becomes available, it proceeds to complete the pending write operations resulting in a substantial reduction in failed operations. Naturally, the addition of the FIFO and the associated control logic results in an increase in area. Therefore, it is essential to properly size the FIFO and evaluate the optimal trade-off between performance improvement and are overhead.