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Evaluation and Integration of a Machine Learning-Based Macro Placer: Impact on Physical Design Flow and Quality Metrics

Chiara Spalluto

Evaluation and Integration of a Machine Learning-Based Macro Placer: Impact on Physical Design Flow and Quality Metrics.

Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2025

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Abstract:

The macro placement step in physical design remains one of the few stages still executed manually by engineers, despite being time-consuming and repetitive. This thesis investigates the automation of this process through the use of a machine learning-based macro placer tool developed in-house at Qualcomm Incorporated. The primary objective of this work is to evaluate the quality and impact of tool-generated macro placements in comparison to traditional manual methods. The thesis is structured to provide both theoretical and practical context for this work. The first chapter introduces the technology scaling trend in the VLSI industry and highlights the growing need for Electronic Design Automation (EDA) solutions, such as the macro placer tool investigated in this work. The second chapter presents a review of the physical design flow, with an emphasis on key metrics and terminology necessary to interpret the experimental results. The third chapter focuses on mixed-size placement, outlining existing solutions in the literature with particular attention to DREAMPlace and ePlace-MS. The fourth chapter evaluates the quality and impact of tool-generated macro placements relative to traditional manual methods, presenting how the tool was integrated into the team's existing workflow via automation. This facilitates broader adoption and demonstrates the value of machine learning in advancing automation within the physical design process. The results demonstrate that the macro placements obtained using the tool consistently achieved quality-of-results (QoR) metrics, such as utilisation, leakage power, and timing, comparable to, and sometimes surpassing, those obtained by experienced engineers. These findings validate the potential of a wirelength-minimising approach as a viable alternative to current heuristic manual methods.

Relatori: Maurizio Martina
Anno accademico: 2024/25
Tipo di pubblicazione: Elettronica
Numero di pagine: 80
Soggetti:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: Nuovo ordinamento > Laurea magistrale > LM-29 - INGEGNERIA ELETTRONICA
Aziende collaboratrici: Qualcomm Technologies Incorporated
URI: http://webthesis.biblio.polito.it/id/eprint/36514
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