Una metodologia efficiente per il test di un SoC basato su microcontrollore, con particolare attenzione alla copertura della memoria Flash integrata. = An efficient approach for testing a microcontroller-based SoC, with focus on embedded flash memory coverage.

Modern microcontroller-based System-on-Chip (SoC) designs represent an increasingly common integrated solution in industrial applications. They are characterised by the integration of multiple peripherals and memory units on a single silicon substrate. In this context, embedded Flash memory are among the most critical components, and testing them presents significant technical challenges. This study, developed in collaboration with STMicroelectronics, proposes an alternative testing methodology to the more common BIST (Built-In Self Test) based techniques. Unlike traditional approaches, it does not require dedicating chip area exclusively to testing functions and minimises data transfer to and from the chip, which is typically limited by the throughput of serial interfaces (such as JTAG) used for testing. The work begins with an architectural analysis of microcontroller-based SoCs, including an introduction to Flash memory technologies (NAND and NOR). It examines the limitations of conventional testing methods using BIST or the traditional JTAG interface, which suffer significant speed constraints, and instead favours the proposed solution based on firmware executed directly by the processing core. The development phase involved implementing test algorithms in the IAR Embedded Workbench environment, optimised to fully leverage the computational capabilities of the Cortex-M4. Functional simulation performed with Cadence SimVision validated the algorithm's behaviour before prototyping. Porting the system to a Xilinx Virtex-7 VC707 FPGA platform was a crucial step for hardware/software verification, while final testing was performed on Teradyne ETS-800} ATE. The results show significant advantages in multiple areas: - Performance-wise}, running firmware on the Cortex-M4 at 144MHz reduced testing time by over 14 times compared to data transfer via JTAG (10 MHz), the most commonly used interface for testing operations. This translates to a substantial reduction in production costs, particularly relevant in high-volume industrial contexts. - The optimised integration of professional tools (IAR, SimVision, Xilinx, ETS-800) throughout the development chain enabled a consistent and efficient workflow while drastically reducing bugs during the device's production testing phase. Thus, this approach stands as a complete and cost-effective solution for testing Flash memory in industrial applications. It demonstrates how the smart use of existing SoC computing resources can overcome the limitations of traditional methodologies, delivering measurable benefits in both quality and production efficiency.