Modern microcontroller-based System-on-Chip (SoC) designs represent an increasingly common integrated solution in industrial applications. They are characterised by the integration of multiple peripherals and memory units on a single silicon substrate. In this context, embedded Flash memory are among the most critical components, and testing them presents significant technical challenges. This study, developed in collaboration with STMicroelectronics, proposes an alternative testing methodology to the more common BIST (Built-In Self Test) based techniques. Unlike traditional approaches, it does not require dedicating chip area exclusively to testing functions and minimises data transfer to and from the chip, which is typically limited by the throughput of serial interfaces (such as JTAG) used for testing.