This report describes my Master’s Thesis internship project from February 5th to August 2nd, 2024, which consists of implementing a Diagnostic Flow for FinFET SRAM memories. The aim is to improve the yield of manufacturing process in RFC division of the STMicroelectronics company. To achieve this, the project involved integrating and automating the use of STAR Yield Accelerator software from Synopsys to build Memory Diagnostic Patterns, to verify their correct functionality and to validate the extraction of failure information on ATE before providing the methodological solution to Product & Test Engineers for debugging chips in the manufacturing process. Key tasks included the generation of a Stop-On-Nth-Error (SONE) Bitmap Diagnostic Pattern to localize memory defects within the SoC, the emulation of the behavior of such diagnostic patterns with different injected errors, and the validation of the correct physical localization of detected memory errors from Automatic Test Equipment (ATE).