Development of demo designs for VE2302-DK based on AMD Versal Edge adaptive SoC VE2302

The AMD Versal™ architecture is a heterogeneous compute platform that combines programmable logic (PL), processing system (PS), and AI Engines-ML (AIE-ML), along with leading-edge memory and interfacing technologies. The Versal™ adaptive SoCs family delivers powerful acceleration to support a variety of applications in embedded systems. This thesis aims to develop a demo design for VE2302-DK by Avnet, based on AMD Versal Edge adaptive SoC VE2302. This design consists in a Linux-based system running on AI Engine, PS, and PL. The design implements a simple image processing system based on the bilinear interpolation algorithm, which can be used, for example, as a pre-processing stage for AI models. The AI Engine domain contains a graph consisting of a bilinear interpolation kernel. The PL domain includes data movers between the global memory and the AI Engine-ML, along with an RTL IP that pre-processes image pixels before they are elaborated by the AI Engine kernel. The PS domain contains a host application that controls the entire system. Despite the final target device being the VE2302-DK, the platform on which this system was targeted and tested is the AMD Versal™ AI Edge Series VEK280 Evaluation Kit. Indeed, the VEK280 board is based on a SoC of the same Versal family (the VE2802), which has the same architecture and a larger number of available resources. In the first part of the thesis, the two involved platforms are described, and a brief analysis of the architecture of the Versal SoC is provided. This part is followed by a description of the bilinear interpolation algorithm, to explain the implementation choices. The second part describes the individual system components: AI Engine-ML kernels, HLS kernels, and RTL IP in programmable logic, and host application. The focus of this section is mainly on AI Engine programming. This part also illustrates the integration of an RTL IP in this heterogeneous environment, along with the interfacing rules that must be followed. The interaction between the AI Engine-ML devices and the RTL IP is analyzed by considering two different design approaches. In the first case, IP and AIE-ML operate sequentially, without direct interaction. The IP fully processes the input frame and writes the output data to DDR before the AIE execution begins. In this approach, the AIE-ML and RTL kernel exchange data using buffers in global memory. In the second design, the IP and AIE-ML work concurrently. The IP provides data to the AIE in packets via an AXI Stream interface, and the AIE processes data between the reception of each packet. The outcomes obtained from hardware emulation on an x86 host machine and from synthesis and testing on the target hardware are presented. The results are described in terms of performance and resource utilization. Furthermore, an alternative implementation using only AI Engine-ML is explored, demonstrating the feasibility of a purely AI Engine-based approach. Overall, this thesis demonstrated the implementation of a bilinear interpolation system on the AMD Versal™ AI Edge platform, integrating AI Engine-ML, programmable logic, and the processing system, considering different design approaches. The result is a reference design that can be used by the final users to explore the platform's heterogeneity and the powerful performance of the Versal devices.