Design and integration of a RISC-V based accelerator for Ascon

Ensuring privacy and data protection has become a paramount concern nowadays, especially in constrained devices that, due to their nature, are not able to implement complex standard cryptographic algorithms. This is the field of lightweight cryptography, algorithms made specifically to balance security with efficiency, ensuring that all systems can safeguard data without hindering performance. The newly appointed standard is the Ascon family, which is a group of algorithms that share the same core function to perform a variety of functions, spanning from authenticated encryption with associated data (AEAD) to hashing and extendable output functions (XOF). This work is focused on improving the performance of Ascon algorithms, through the design in steps of a customized accelerator. The first optimization is performed through an instruction set extension of a generic RISC-V processor, iteratively finding out the bottlenecks of the algorithm and solving them. In the end, through unrolling, the final processor can compute the algorithm up to ten times faster than the baseline, a result that is five times faster than other implementations in literature. Meanwhile, the best compromise between occupied area and speed is characterized by a speedup of x8.6 from the reference implementation, with a marginal area increment of the processor (+20%). The acceleration performed until now has resulted in an application-specific processor, which has the fastest computation, but the nature of the processor was changed. In order to maintain the original structure, the following step is to design a coprocessor which will still be integrated into the pipeline of the core, but it communicates through a specific interface. The obtained speedup reaches up to x5.8 times faster than the baseline in the hashing algorithms, and x3.6 of the AEAD.