Hardware Acceleration of AdderNet via High-Level Synthesis for FPGA

Convolutional Neural Networks (CNNs) are widely used for machine learning tasks but often come with high computational costs due to their reliance on resource- intensive Multiply-ACcumulate (MAC) operations. As a more efficient alternative, AdderNet (AddNN) replaces these MAC operations with simpler Sum-of-Absolute- Difference (SAD) operations, employing an ℓ1-norm-based approach. While this architecture reduces computational expenses, it has not yet achieved the same level of hardware optimization as CNNs, particularly in areas such as effective quantization, accelerator design, and efficient use of FPGA resources like DSP slices. This thesis presents an efficient quantized implementation of the AddNN ResNet20 architecture using an 8-bit fixed-point quantization scheme. Developed with the Brevitas framework, this approach significantly reduces memory usage and computa- tional overhead, enabling efficient deployment on FPGAs. The model’s hyperparam- eters were fine-tuned and trained on the CIFAR-10 dataset, achieving an accuracy of 86.61%. The architecture was represented in a custom QONNX format to detail the layers, input-output quantization, and connections. Additionally, a tailored high-level synthesis (HLS) code generation pipeline was created to transform the Python-based model into an FPGA bitstream using Vitis HLS. The implementation and validation of this architecture were demonstrated on the Kria KV260 FPGA board, utilizing ResNet20 on the CIFAR-10 dataset to showcase the efficiency of the proposed solution. The contributions of this research aim to enhance the performance and flexibility of AddNNs in embedded systems, particularly those leveraging FPGA hardware, through innovations in both architectural design and implementation methodologies.