Spiker-V: bringing Neuromorphic Intelligence at the edge through the optimized integration of a SNN Hardware Accelerator with a Low-Power RISC-V Processor

Integrating Artificial Neural Networks (ANNs) into edge devices enables real-time AI capabilities directly at the network's periphery. This iscrucial in domains like autonomous vehicles, industrial automation, and healthcare, where ANNs can process data locally, reducing latencyand power consumption while enhancing privacy. Specialized hardware accelerators for Spiking Neural Networks (SNNs) offer a promisingparadigm, mimicking biological neurons for dynamic data processing. However, the effectiveness of the accelerator hinges on its ability tobe adequately controlled and configured. Moreover, it must efficiently read data from sensors and store results back in memory in real-time. This thesis aims at the development of an optimized interface between a custom hardware accelerator for SNNs and a RISC-Vprocessor, based on the PULP architecture. The system will be deployed on FPGA, to obtain a fully autonomous, low power system able toperform real-time inference in resource constrained edge applications.