Software-based test images for in-field fault detection of hardware accelerators

The increasing adoption of artificial intelligence (AI)-based systems has led to growing concerns about their deployment in safety-critical environments. Industry standards, such as ISO 26262 for the automotive sector, mandate the detection of hardware faults during the device's canonical operations. Similarly, new standards are emerging to address the functional safety of AI systems (e.g., ISO/IEC CD TR 5469). Hardware solutions have been proposed for in-field testing of the hardware executing AI applications, nevertheless these approaches can increase hardware costs and may potentially negatively impact the strive for performance maximization, especially in applications involving Convolutional Neural Networks (CNNs) for image processing tasks. This thesis inquire into a methodology for creating high-quality test images that can be interleaved with the normal inference process of a CNN executing in the realm of edge devices, specifically exploiting the blend of the open-source configurable and extendable X-HEEP platform, designed to support the exploration of ultra-low power edge accelerators, and the Xilinx PYNQ-Z2 board. Image Test Library (ITL) has been developed in order to facilitate the on-line testing of a 32-bit integer multiplier. The proposed methodology does not necessitate modifications to the existing CNN, thereby avoiding costly memory loading operations, as it effectively leverages the CNN's existing structure. Additionally, the proposed ITL requires minimal test application time and memory space for storing the test images and corresponding golden test responses. The ITL is specifically designed to leverage the convolution operation, which involves multiply-and-add computations between an input image and a set of filters. Since the primary goal is to maintain the original CNN structure, weights must remain unchanged, while the input images are the only elements which can be altered. Consequently, test patterns for the multiplier must be created using Automatic Test Pattern Generation (ATPG) techniques, with the pre-trained network weights serving as constraints. These generated test patterns are then strategically placed in specific areas of the input image to ensure that the multiplier will process them with the corresponding weights used as constraints. Finally, the image containing the test patterns, called faulty image, is tested during the fault injection phase to ensure that its content allows to successfully propagate the fault along the network, resulting in a wrong class prediction. Experimental results demonstrate that the proposed methodology achieves 84.97% test coverage on the hardware unit under test, utilizing 22 test patterns generated during the ATPG phase for the quantized (int8) LeNet-5 CNN.