As the complexity of modern Integrated Circuits (ICs) grows, ensuring that these designs function as intended becomes increasingly challenging. Verification plays a crucial role in this process by detecting bugs early, when they are significantly less costly to fix. Traditional verification methodologies, such as manual simulations, have struggled to keep pace with the growing complexity of ICs, particularly in functional verification. To address these challenges, the Universal Verification Methodology (UVM) has emerged as a standardized framework, enabling scalable, modular, and reusable verification environments, thus overcoming many of the limitations of older approaches. This thesis presents the functional verification of a high-performance memory controller, a key component embedded in a hardware accelerator IP.