Scalar Cryptography Extensions for STxP5
Marco Chiarle
Scalar Cryptography Extensions for STxP5.
Rel. Guido Masera. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2024
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Abstract
The fast evolution of digital technology has brought in an era where security is not negligible, especially in the world of the embedded systems. As Cyber threats are always more sophisticated, the demand for robust cryptography solutions is increasingly high. In this context, the RISC-V instruction set architecture (ISA), with its open-source form and modular design, presents a fertile ground that it is perfect for the future development. RISC-V has started in 2010, from the Parallel Computing Laboratory at the University of California, Berkeley, under the leadership of Professor David Patterson. RISC-V ISA is completely free and open-source, and It is based on the Reduced Instruction Set Computer (RISC) principles.
This thesis is focused on the integration of cryptography extensions within the RISC-V ISA, with the dual objectives of increasing the security capabilities of embedded systems and also enhancing the perfomance
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