Scalar Cryptography Extensions for STxP5

The fast evolution of digital technology has brought in an era where security is not negligible, especially in the world of the embedded systems. As Cyber threats are always more sophisticated, the demand for robust cryptography solutions is increasingly high. In this context, the RISC-V instruction set architecture (ISA), with its open-source form and modular design, presents a fertile ground that it is perfect for the future development. RISC-V has started in 2010, from the Parallel Computing Laboratory at the University of California, Berkeley, under the leadership of Professor David Patterson. RISC-V ISA is completely free and open-source, and It is based on the Reduced Instruction Set Computer (RISC) principles. This thesis is focused on the integration of cryptography extensions within the RISC-V ISA, with the dual objectives of increasing the security capabilities of embedded systems and also enhancing the perfomance. The development and evaluation of a specialized cryptography extension for the RISC-V ISA take center stage, considering the crucial balance between power consumption, area, and performance. Indeed the thesis presents a comprehensive analysis of the design, implementation, and optimization of the cryptography extensions for the RISC-V processor, with a focus on the extended ISA. Utilizing tools provided by STMicroelectronics, the thesis goes through the entire process from specification, code writing, analysis and synthesis to testing, ensuring a comprehensive approach to the development of cryptography extensions. The outcome of this research goes over the academic theory, offering a contribution to the field of embedded system security. It is a base for future STMicroelectronics projects on RISC-V, delivering a complete development for secure, efficient, and cost-effective cryptography implementations within the RISC-V ecosystem.