UVM verification for RISCV extention

SOC Verification.This thesis presents the development and implementation of a comprehensive verification environment for a RISC-V extension architecture using the Universal Verification Methodology (UVM). The primary objective was to create a robust, flexible, and reusable framework to thoroughly verify the functionality of a RISC-V core implementation, including base ISA, extensions, and proprietary additions. The verification strategy addressed the challenge of ensuring the correctness and reliability of complex processor designs, crucial in the context of RISC-V's growing adoption.