A Survey: Hardware Neural Architecture Search On FPGA/ASIC

Deep learning (DL) systems are revolutionizing technology across various fields. These breakthroughs are driven by the availability of big data, tremendous growth in computational power, advancements in hardware acceleration, and recent algorithmic innovations. The rapid development of deep learning has spurred demand for efficient hardware implementations capable of handling complex neural network architectures. Due to their flexibility and performance efficiency, Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs) have become key platforms for accelerating deep learning tasks. To fully harness the potential of these hardware platforms, researchers have turned to Neural Architecture Search (NAS), a promising paradigm that automates the design of optimal neural network architectures optimized for specific hardware constraints. Recently, integrating hardware awareness into the search loop (i.e., HW-NAS) has attracted many researchers and opened up exciting new research directions. Some efforts in HW-NAS have already demonstrated state-of-the-art results, achieving a balance between accuracy and hardware efficiency. Neural architecture search on FPGAs and ASICs involves exploring a wide design space to discover architectures that maximize performance metrics such as accuracy, speed, and energy efficiency. This survey comprehensively examines methodologies, challenges, and trends in hardware-aware NAS, focusing particularly on implementations on FPGAs and ASICs. HW-NAS consists of three key components: first, the search space defines the types and structures of DL architectures to form effective networks. Second, search algorithms employ multi-objective optimization strategies such as evolutionary algorithms or reinforcement learning to sample network architectures. Finally, evaluation methods calculate DL performance and efficiency metrics, such as accuracy and hardware specifications on target platforms. HW-NAS addresses multi-objective optimization problems aimed at balancing accuracy, inference latency, and energy consumption constraints. Evaluation results guide search strategies towards promising architectures within the search space. HW-NAS can provide a range of advantageous solutions rather than a singular optimal solution, making multi-objective optimization strategies particularly valuable in edge computing scenarios. This survey primarily reviews literature on hardware-aware NAS algorithms targeting ASICs and FPGAs. HW-NAS requires interdisciplinary knowledge including device-specific compilation, hardware microarchitecture, neural network design, and efficient NAS algorithms. While many AutoML and NAS review papers focus on theoretical concepts of architecture search, few extensively discuss hardware-based approaches. This survey covers research reported in literature from 2019 to 2024, providing a concise overview of HW-NAS. The review is divided into several sections. In Section III, we focus on relevant HW-NAS search spaces. The search space consists of neural network architectures that determine how neural network operators are connected to form effective networks and which operators are allowed. In Section IV, we briefly outline common search strategies and how they explore the search space by sampling candidate neural network architectures. In Section V, we discuss how evaluation methods assess the performance of architectures across various metrics. We hope this review will be helpful to those interested in the latest advance