Generation and verification of timing constraints within the digital implementation flow for the Static Timing Analysis of ASICs

Starting with an RTL (Register Transfer Level) description of a SoC (System on Chip) is the first step towards developing a complete and functional product. This complex process, known as the Front-to-Back (Fe2Be) flow, encompasses a series of critical steps that aim to obtain a final working product. Timing constraints are the inputs for Static Timing Analysis (STA), which relies on them to assess if a circuit satisfies the necessary timing specifications for correct functioning. They play a crucial role in this transformation, as they are key to directing the logic synthesis process. The latter is a fundamental step in the digital implementation procedure, converting the RTL description into a digital logic network comprised of fundamental components such as AND gates, OR gates, adders, flip-flops and so on. This conversion is not merely a translation but an optimization challenge, predominantly influenced by the available logic cells provided by the chosen technology and the imposed timing constraints. The ultimate objective is to obtain a netlist that optimally balances area and power consumption while satisfying the customer's timing specifications. The precision of timing constraints is essential, as they significantly affect the Quality of Results (QoR) in terms of performance, area, and power efficiency. Inaccurate timing constraints can lead to a device that fails to function correctly or one that unnecessarily expends power and occupies more area than required. The target of this thesis, developed in partnership with STMicroelectronics, is to conduct a comprehensive analysis of the state-of-the-art of TCM (Timing Constraints Manager) tool from Synopsys. This tool is employed in the creation and validation of a solid methodology for generating and verifying timing constraints in a System on Chip. Using two ASICs (Application-Specific Integrated Circuits) of medium to high complexity, known as the Machiavelli and Sheldon projects, as case studies, this research aims to develop a reliable method for timing constraints management through the application of TCM. This tool introduces new functionalities that have not been previously applied to the creation and validation of timing constraints. It includes formal verification methods to ensure the accuracy of timing exceptions, which are essential yet sensitive constraints. When applied correctly, they can greatly assist in meeting the objectives of static timing analysis. However, any inaccuracies in these constraints could result in silicon failures. In summary, the overall approach taken aims to improve the formulation of timing constraints within the digital implementation process. This method tried to exploit the tool's extensive functionality as much as possible to uncover both the capabilities and limitations of Timing Constraint Manager (TCM). Indeed, the tool has the potential to simplify the process of writing timing constraints significantly, saving time and increasing the precision of the results. Nevertheless, it should be enhanced in specific aspects, which this thesis will detail.