System Level Test methodologies for complex timer peripherals

The thesis work will focus in the generation of System Level Test procedures aiming at complementing the weaknesses of structural test methods. The case of study will be a complex timer module of an industrial System-On-Chip. This research will show different approaches adopted to produce programs suitable to test that parts of the component that are less stressed, and that can only be covered by specific functional procedures. Each method is described and detailed in order to provide a clear understanding of the motivations behind its choice, exploring solutions that are consistent with the analysis of the results obtained by the simulation to which each test is subjected.