Development of a high-throughput floating-point CORDIC architecture for automotive applications

The computation of complex functions such as the trigonometric and hyperbolic ones is usually performed either implying large lookup tables or by long software routines. However, the suitability of both solutions strongly depends on the specific application. For example, the former one, storing the results inside a memory, can be very fast and efficient when accuracy is not paramount, but it can lead to prohibitive area occupations. On the other hand, the latter solution exploits polynomial approximation to provide precise results, but it forces the processor to spend a large amount of time waiting for its completion. As a result, the two approaches cannot be adopted for high-accuracy and low-latency applications. In this context, the integration of a dedicated accelerator can be very effective, since it lets the processor offload the execution of such functions. This work, therefore, presents the design and implementation of a unit that, exploiting CORDIC algorithm, is able to reach a large variety of executable functions, albeit maintaining high levels of accuracy and throughput. In its unified version, CORDIC algorithm can compute trigonometric and hyperbolic functions, multiplications, divisions and plane rotations by only performing, iteratively, shift operations and additions. This makes clear its ability to reach low latencies, but also highlights the need for a quite large number of iterations to ensure the desired accuracy. However, being CORDIC architectures particularly prone to unrolling and pipelining, this does not represent a major issue. The main drawback is, then, its strict bond with fixed-point representation, which makes it unsuitable for high precision applications. To overcome this limitation, the proposed design fuses CORDIC algorithm with floating-point arithmetic, thus allowing it to reach the desired accuracy. This extension can follow two strategies, that is either to adopt floating-point arithmetic blocks or to opportunely convert inputs and outputs to have an internal fixed-point pipeline. For this design, the latter solution has been chosen, since it allows to have much faster stages. However, this choice led to the need for specific arrangements to fuse floating-point-specific concepts (Infinities, NaNs) with fixed-point arithmetic. In this work, two binary IEEE-754 formats have been considered, that is single and half precision, since both of them represent a good trade-off between precision and speed. The architecture description process has been carried out in SystemVerilog starting from each computational stage and then moving to the whole system, having high throughput and accuracy as main focuses. This let it not only satisfy the required working frequency of 100 MHz, but also reach a maximum one above 1 GHz. The design has, then, been tested and synthesized, obtaining promising results in terms of error, area, power and speed. In addition, the unit has been integrated as a peripheral in the open-source X-HEEP platform, providing, as expected, faster execution times, compared to the software-based routines, without trading accuracy for performance. In conclusion, the proposed design has shown to be a viable solution for low-power, high-performance and high-precision applications and future works may focus on the further reduction of power consumption, for example by means of clock gating, on the integration of other standard or custom floating-point formats or on the execution of more complex functions obtained by exploiting the existing ones.