Concept study of controlled normal load for the spotless unit

As the consumption of high-tech microchips keeps rising and the size of the transistors keeps decreasing, the tools required to manufacture chips become more and more complex. In an industry where efficiency and quality at nanoscopic level is key, every feature that could potentially improve the existing tool is important. This thesis covers the concept study of a controlled normal load for the spotless unit, conducted at the company ASML. Spotless is a system within the ASML DUV lithography machines used for cleaning the wafer tables and extending their lifetime through reconditioning. The study investigates the potential benefits of an additional degree of freedom for spotless, that could be integrated into future machine generations. The first segment provides a thorough analysis of the impact of normal load on spotless operations, drawing on prior studies and experiments but also on new research and experiments undertaken for this project specifically. The outcomes and insights from this analysis lay the foundation for a list of requirements used in the subsequent design study. The second part presents design options, detailing their strengths and weaknesses. The thesis then draws conclusions and recommendations derived from the comparison of the designs and results from experiments, considering the risks and benefits of the implementation.