Quantization Reconstruction Based LDPC Decoders

Nowadays, digital communication requires extremely high standards in terms of latency for channel decoding. Therefore, different techniques are investigated to combine high frequency within limited hardware resources of FPGAs and ASICs and as a result, there is a preference for decoder with low bit width. The Low-Density Parity-Check (LDPC) codes have found wide use in multiple implementation contexts, especially in wireless communication system for its reliability in correcting errors while maintaining a high code rate. The focus is concentrated on keep good correction capacity by using a reduced bit width, with the intention to meet the requirements of low latency and area. Several design solutions to reduce bit width have been explored, and one in particular, which relies on the use of Quantization and Reconstruction units, has shown good results in terms of the trade-off between complexity and performances. The work presented in this master thesis offers an in-depth study on the analysis of the Variable Node (VN) which build the LDPC decoder, in particular on the use of lookup tables (LUTs) or Thermometric blocks for the Quantization and Reconstruction block. All the results and the syntheses report are obtained using a 65 nm technology library. The differences in the occupied area and the critical path offered by the two implementations were analyzed giving an overview on the trade-off that is observed on them when the parameters involved vary, such as internal bit width of VN, external bit width and degree. The study of Variable Node proceed by looking at the performances provided by different implementation methodologies, one with data handled sequentially, or a parallel representation with high throughput. Finally, the focus is on an complete architecture with all Variable Node instantiated according to the degree profile described by the interconnection matrix H, providing an overview of all VNs implemented at the complete decoder level.