Currently, the increasing demand for computation speed requires advanced technology to generate the results at a relatively high performance. In this case, the FPGA platforms could be one possible choice due to their possibility to accelerate computation based on the highly optimized critical part at the hardware level, its parallelism, and low latency, which can be more efficient compared with general-purpose CPUs. By exploiting High-Level Synthesis (HLS), FPGA platforms can deliver an optimized hardware implementation with relatively low design effort. HLS accepts as input high-level programming languages for example C++, and by exploiting user-written pragmas and configuration directives, it can automatically generate the hardware implementation with various optimized architectures.