5G protocol stack downlink simulation acceleration via Xilinx Alveo U280 FPGA

In today's world, the mobile network is already recognized as one of the most critical infrastructures that a nation must maintain. Recent events such as the appearance of IoT systems have also demonstrated that the ability to swiftly exchange information among people and devices has beneficial effects on the economy, security, and overall efficiency. It comes as no surprise that many countries have intensified their efforts to invest in improving communication technology, and these efforts have led to significant advancements. 5G communication is the most recent step in wireless standards with which it is possible to reach higher multi-Gbps peak data speeds, extremely low latency, more reliability, a greater network capacity and increased availability. To gain a better understanding of the optimal placement for 5G cell towers, it is cost-effective to conduct preliminary testing before installing the antennas. In partnership with TIM, this thesis project explores the creation of an FPGA accelerated simulator that can efficiently facilitate these required tests within a short timeframe. The FPGA used is the Xilinx Alveo U280, which is a high-performance accelerator card designed for data center and enterprise applications. An FPGA device is better suited to address computationally intensive problems compared to a general-purpose CPU due to its ability to be configured by the user after manufacturing, making it more specific and efficient. The FPGA kernel is divided into five main blocks: Modulator, Oversample Filter, Channel Model, Downsample Filter, and Demodulator. Each of these blocks was implemented in C. By utilizing the Vitis HLS (High-Level Synthesis) tool in conjunction with specific pragmas for kernel configuration, it is possible to translate the high-level C code into synthesizable RTL (Register Transfer Level) code, which serves as the required low-level hardware description for FPGA implementation. Vitis HLS is therefore the tool capable of compiling the C code into a Xilinx object (.xo) file. The Vitis compiler is the one responsible of linking the .xo file previously produced with the hardware platform library to create a device executable file (.xclbin). Such file is the final device binary (bitstream) that will then be uploaded into the FPGA device to configure. A critical aspect of the thesis work involved managing the performance and area trade-offs for the designed kernel blocks. It was essential to maximize hardware utilization without exceeding its capacity. To achieve this, the approach taken was to leverage all three SLRs (Super Logic Regions) of the FPGA device, effectively breaking down the problem into separate, independent, and parallelizable tasks. The input and output size of the kernel for this device is a 54,770 x 32 complex floating-point matrix. Since each row operates independently of the others, it is possible to use each SLR to concurrently simulate one row, significantly accelerating the simulation time.