Exploring the Razor Approach for Better Than Worst-Case Design in Latency-Insensitive Digital Circuits

The relentless advancement of technology in recent years has led to an exponential growth in the demand for computing power across various sectors. From artificial intelligence to data analytics and complex simulations, the computational requirements have consistently pushed to the limit the capabilities of existing hardware. In the last years digital circuits have meet these performance requirements by architectural improvements and by technology scaling, but as semiconductor technology continues to shrink and more transistors are integrated on a single chip, power dissipation has emerged as a critical bottleneck. Moreover, as feature sizes continue to shrink, the sensitivity of circuit behavior to small deviations in manufacturing processes, supply voltage, and operating temperature (PVT variations) becomes more pronounced. This poses a formidable challenge for circuit design, as the traditional design methodologies that rely on worst-case scenarios may result in sub optimal performance or excessive power consumption due to its overly conservative nature. A solution to these problems is a change of design methodology, instead of always considering the worst case to avoid the generation of errors in the circuit, it is possible to design considering a better than worst case condition, to allow the generation of errors, and implement a method to correct them. Using this new approach the safety margins can be eliminated, therefore, if the correction of errors does not introduce an overhead greater than the gains brought by the removal of safety margins, a meaningful increase in efficiency is achievable. A low-overhead, technique capable of detecting and correct errors in general purpose devices exists, it is called Razor, it allows to remove the safety margins and it is able to handle both fast and local variations in circuit performance using error detection cells at the end of the critical paths. Nevertheless the razor approach introduces additional challenges for the design procedure, it requires an accurate study of the circuit's timing and an efficient error recovery mechanism. The objective of this thesis work is to apply the Razor technique to different digital circuits and to tackle the timing violations caused by the introduction of the error detection cells by utilizing a novel optimization flow called Mix & Latch. To reduce the impact on performance caused by the error correction, Razor is applied to latency-insensitive designs, in such designs different block of logic can work concurrently and, at the end of their operations, exchange data between them using synchronous handshakes; an error in a block of logic will slow down only that block while the rest of the circuit will operate without interruptions. The results of the flow are validated using post-layout simulations to evaluate the area and power overhead caused by the addition of error detection and correction to the designs.