Implementation of a RISC-V based microprocessor architecture for NFC communication

This thesis document and the related activities carried on during last few months constitute an experimental HW/SW co-design led by NXP Semiconductor Gratkorn (Austria) in collaboration with Politecnico di Torino and Graz University of Technology, within the context of the project TRISTAN. The EU-funded TRISTAN project aims to further expand and develop RISC-V architecture in Europe so that is able to compete with existing commercial alternatives. This open specification eliminates the need to learn and create unique ecosystems for each processor architecture, increasing productivity, security and transparency. The main goal of this activity is to map on a RISC-V ISA compliant microprocessor sub-system one or more NFC standard decoding algorithms, sharing the computational load between HW and SW thus to achieve a number of additional goals (e.g., in-field reconfigurability, logic count, clock rates, static and dynamic power demands) which have been listed in the requirements specifications of this work item. The microprocessor architecture is based on an OpenHW Group CV32E40X RISC-V high performance core which offers an interface for extending it with a coprocessing unit. The mentioned core was selected for the presence of the so called eXtension InterFace (XIF) which eases the Instruction Set Architecture (ISA) extension to support dedicated DSP operation for performance enhancement. The core is coupled thanks to this interface with a coprocessor in order to perform DSP filtering operations. This work has the ambition to further extend the firmware flexibility to fully support different baud-rates as well as different NFC standards. The actual challenge is performing all the tasks supported in an efficient way, providing an architecture that operates at a feasible clock rate for real-time DSP applications and that ensures a proper trade-off between gate count and power consumption. The future ambition is to provide this module as an off-the-shell block to be integrated into a more complex NFC/RFID Software Defined Radio (SDR) modem.