This thesis document and the related activities carried on during last few months constitute an experimental HW/SW co-design led by NXP Semiconductor Gratkorn (Austria) in collaboration with Politecnico di Torino and Graz University of Technology, within the context of the project TRISTAN. The EU-funded TRISTAN project aims to further expand and develop RISC-V architecture in Europe so that is able to compete with existing commercial alternatives. This open specification eliminates the need to learn and create unique ecosystems for each processor architecture, increasing productivity, security and transparency. The main goal of this activity is to map on a RISC-V ISA compliant microprocessor sub-system one or more NFC standard decoding algorithms, sharing the computational load between HW and SW thus to achieve a number of additional goals (e.g., in-field reconfigurability, logic count, clock rates, static and dynamic power demands) which have been listed in the requirements specifications of this work item.