FPGA-Based Signal Processing Architectures for 5G Wireless Using High-Level Synthesis

The rapid advancement of technology, coupled with the widespread adoption of the Internet of Things (IoT), has driven the quest for novel solutions that significantly improve speed and resource efficiency, surpassing traditional implementations. In hardware design, High-Level Synthesis (HLS) techniques present an efficient avenue for generating hardware designs using high-level programming languages, notably C/C++. HLS tools scrutinize design specifications and autonomously create hardware implementations aligned with performance requirements. The main objective of our research was to accelerate the 3GPP 5G Channel Model. We specifically aimed at enhancing the channel model using High-Level Synthesis (HLS) tools designed for Xilinx and Intel FPGA platforms. Given the complex nature of the project, each team member focused on discrete components of the channel model. My primary contribution centered on the Oversample_Filter section. This component processes a large-sized input matrix using the Upsample function and Matlab's Finite Impulse Response (FIR) function. I first designed the Oversample_Filter in C++ to mirror the Matlab algorithm. Subsequently, I employed Vitis HLS to optimize the C++ code, ensuring optimal throughput to align with other parts of the channel model. In the end, the generated Register Transfer Level (RTL) design was subjected to simulation tests and on-board validation before its incorporation into the channel chain.