Modeling and implementation studies of pixel readout architecture for on-chip processing in High Energy Physics applications

Modeling and implementation studies of pixel readout architecture for on-chip processing in High Energy Physics applications As the complexity of particle detectors in High Energy Physics rises, new approaches to system prototyping become necessary to deal with higher data rates than ever before. The first chapters of this thesis propose an Electronic-System Level approach to be applied to pixel detectors systems, and provide a SystemC framework to carry out architectural exploration at a level of abstraction above RTL. It can be used to study the efficiency of a chosen architecture, while sweeping the parameters of interest and obtaining figures of merit. With this tool, we were able to prototype a read-out chip able to support the hit rates for the next upgrades of the LHCb upgrade. The last part of this thesis details the design flow of an on-chip processing module for the same upgrade, showing how the SystemC framework could be integrated as a starting step in system design for ASICs and how a physical layout could be derived from the abstract model.