Improving Apple Test Chips Efficacy through the Integration of SSN and ICL Automation Flows

The increasing importance of the Design For Testing engineering approach within the silicon industry is exemplified by the need of validating the manufacturing process of electronic devices that have become more complex than ever before. The optimization of test time and efficiency for an ever-growing amount of dies has become the major focus of all tech corporations that strive to deliver higher quality products more frequently at a lower cost. The Apple Inc. team based in Munich is developing pre-production prototypes called "test chips" in order to organize all the output of their manufacturing processes into a flexible hardware arrangement meant for testability purposes. Their building blocks are grouped into clusters, which are the basic functional units for all trials performed on silicon. The essential capability in this context is represented by the capability of dynamically managing different cluster combinations, activating only the selected ones while bypassing the others. The former state of the art of the company consisted of a rigid selection mechanism that did not provide this commodity in a serviceable way. The conception of a modern, automated flow able to render all upcoming architectures compatible with the Streaming Scan Network technology represents an answer to these challenges. In fact, it can be used to streamline the delivery of test data to each node connected inside a common network and seamlessly works in conjunction with the latest market standards. Its implementation requires the development of an auxiliary characterization incorporating a condensed description of the hardware, so that the automated tool of choice offered by Siemens can use it to communicate with the device under test in a more optimized way. After applying several case-specific configurations, the final goal is to generate pattern sets, which are the primary input stimuli ultimately needed to perform the ensuing test runs. The solution presented so far was previously non-existent at the company, and as such both its implementation and its validation constituted the main task of the presented project. Firstly, a central script is responsible for automatically deriving a simplified model of the design required by the utilized software tool. The interface with the user is provided by a set of command line arguments, whereas the principal input resides in a unique data structure that contains all the information used to also define the reference architecture through the most common Hardware Description Languages. The two parallel archetypes represented by the original, complete depiction and the newly obtained schematized arrangement must then be matched against one another as to check for their 1:1 correspondence. Consequently, a whole new automation flow has been developed around trying to prove this identity and writing out the requested testbench files that can be run in order to get a definitive yes/no answer in terms of quality acceptance. The positive impact of the fabricated deliverables can be demonstrated in terms of timing performance, flawless execution and adaptability and opportunity for reuse. In fact, this automated solution is orders of magnitude faster and less error-prone than a handcrafted approach, while its key advantage resides in its adaptability to all future test chip architectures with little to no need for manual intervention. Finally, its outcomes have already been certified within two of the company's current projects and are being extensively used in production.