SystemC Simulation of Extra-functional properties for RISC-V-based systems

Nowadays, the RISC-V instruction set architecture (ISA) is gaining traction among engineers and companies thanks to its royalty-free and open-source nature. Following in the footsteps of highly successful open-source software projects (e.g., Linux, GNU, etc.), RISC-V represents an attractive choice to build an open-source hardware community that actively supports updates and ensures continuous improvement. RISC-V can be used without any fees, making it a cost-effective solution for enabling smart heterogeneous embedded systems, which include sensors and actuators, such as nano-drones, smart assistants, and wearables. In this landscape, the availability of simulation platforms is a key ingredient for making RISC-V based hardware solutions pervasive. Simulators represent a cost-effective and scalable solution that enable rapid prototyping without the need for physical hardware. For these reasons, there is a growing availability of programs designed to simulate entire RISC-V chips. Some options include QEMU, Simulink, Renode, and GVSoC. However, these tools present some limitations. Most of them only simulate the computing core with scarce possibilities to perform system-level simulations. Moreover, they simulate only functional features, with poor support for extra-functional properties such as power consumption. This work tries to address these challenges by presenting a flexible simulator, developed in collaboration with the University of Bologna, in the context of the TRISTAN European project. The simulator combines the SystemC/SistemC-AMS physical and continuous time modelling capabilities with GVSoC, a lightweight and flexible RISC-V functional instruction set simulator. The simulator takes two inputs. The first is a high-level description of the system in JSON which is then internally translated into SystemC/SystemC-AMS components through a template-based code generator written in Python. The second is the C code to be simulated on the RISC-V core through GVSoC. In this thesis, we focus on the co-simulation of the functionality and power consumption of the system. Nonetheless, the code has been developed to be general, allowing the support of additional extra-functional properties (e.g., temperature, reliability) with minimal intervention. Overall, the thesis successfully demonstrates how to integrate SystemC/SystemC-AMS simulations of extra-functional properties with a RISC-V functional simulator.