Development of a fault injection methodology and fault coverage analysis for a safety-relevant block

As electronic products become integral to daily life, their presence in safety-critical automotive systems becomes pervasive. The International Standard Organization (ISO) 26262 standard outlines guidelines for establishing a good level of safety in automotive System-on-Chips (SoCs) but, despite the adherence to this standard, operational failures still remain possible, prompting the need for Safety Mechanisms (SMs) to reduce random hardware faults. Nevertheless, SMs must go through a fine verification and validation phase, often involving fault injection, to ensure that they are compliant with the standard and they work as intended. This thesis examines the unique challenges posed by safety-critical SoCs and their SMs within the automotive sector. In particular, it proposes a comprehensive in-house fault injection and analysis tool named Fault Injection e Verification Component (FIeVC ) to ease the development of safety-critical components in Bosch SensorTec (BST), highlighting its benefits and potential integration challenges. The FIeVC tool is developed in Specman e and leverages parallel fault simulation to compare a fault-free system and a faulty counterpart for mismatch detection, using four main components: the Monitor, the Sequencer, the Bus Functional Model (BFM) and the Analyzer. The thesis also details the development of preliminary scripts needed for generating fault lists and modifying testbenches, both crucial aspects of a successful fault simulation. The tool is evaluated using an accelerometer datapath from a Micro Electro-Mechanical Systems (MEMS) Inertial Measurement Unit (IMU) platform developed by BST. The tests conducted to assess the FIeVC performance, show that the tool takes 68% less time to perform a full fault simulation compared to traditional tools while keeping the Test Coverage (TC) level basically unchanged. These substantial simulation time improvements are mainly obtained by making use of the parallel algorithm and the advanced Specman e Testflow feature to implement the most critical and time-consuming task, the Design Under Test (DUT) reset procedure.