Automating Safety Mechanisms insertion providing standard SIL compliance in digital circuits

Functional Safety is a mandatory requirement for different industry sectors, like automotive, aeronautics and aerospace. It requires a system to be able to detect an error, which can be systematic, human-driven or caused by operational and environmental stress, and recover the correct functionality of the system. Functional safety prioritizes the health of humans interacting with the system in a direct or indirect way. Chip designers and companies, working for the development of products in these sectors, are thus required to achieve different compliance levels, which are specified by industry-specific standards. As an example, for the automotive domain, the ISO 26262 standard is used, which provides four different compliance level. Going from the ASIL A, the lowest rating, to ASIL D, which is the highest rating requiring >99% fault coverage. Compliance is achieved by the implementation of Safety Mechanisms on the different units of the system. The most common ones are Triple Modular Redundancy and Lockstep. Implementing these mechanisms, however, can be quite expensive, since they are typically achieved by applying them to the whole system. Optimization is thus required and the exploration of different solutions is needed. Performing this space of solutions exploration can be time consuming, since typically for the different components to harden, a custom solution needs to be implemented from scratch, going from the RTL to the different verification and implementation stages. Also, proper statistics on the achieved level of fault coverage and thus safety compliance need to be generated. An automated solution has been developed by Synopsys called Safety Specification Format. It is fully integrated with other tools developed by Synopsys related to Safety mechanisms. Having an automated solution provides different benefits. They go from having an improved traceability of the most error-prone and time consuming tasks, like RTL generation and verification, to the reutilization of already implemented solution IPs in a scalable way, improving the overall quality of results and reduce the time-to-market of a product. It can be used in automotive designs, to achieve up to ASIL D specification compliance, but also in other industrial sectors, like industrial IoT. The target architecture used in this Thesis project, is the OpenHW CVA6 Ariane CPU, since it's a processor that can be used in real world applications. In fact, the CVA6 is a 6-stage, single-issue, in-order CPU which implements the 64-bit RISC-V instruction set. It fully implements I, M, A and C extensions while also providing an implementation of three privilege levels M, S, U to fully support a Unix-like operating system. It has a configurable size, separate Translation Lookaside Buffers and branch-prediction unit, composed by a branch target buffer and a branch history table. OpenHW also provides a verification suite for this processor line, called Core-V-Verif, which has been used as a starting point to the development of an FMEDA process on this processor. Different state of the art Synopsys' tools have been integrated in the flow, starting from VCS and VC-Z01X, through RTL-Architect to the FuSa suite to support the experiments.