Definition of a verification flow for High-Level Synthesis IPs: Case study on functional coverage applied to High Level Synthesis blocks in a C++ and Universal Methodology environment

High-Level Synthesis (HLS) tools are becoming increasingly important in simplifying the design process for digital circuits due to the growing complexity of digital design. These tools enable designers to use high-level programming languages to develop Register Transfer Level (RTL) circuits, thereby reducing design complexity and time-to-market. With HLS, designers can develop algorithms and use the tool to explore various hardware implementations, such as adjusting the number of pipeline stages, loop unrolling, and meeting area and latency constraints. However, the use of HLS requires the establishment of verification flows for both high-level design and RTL generated by the tool. This thesis, conducted at STMicroelectronics, builds on the work of Jiangxi Wu and Giacomo Spinello, who developed the verification plan for the high-level Design Under Test (DUT). The aim is to complete the verification plan by introducing functional coverage into a tool-generated Universal Verification Methodology Framework (UVMF) and the high-level testbench. The flow was implemented using Siemens EDA Catapult Synthesis tool, which translates the high-level design to RTL and generates a UVMF to test the design. The testbench applies random inputs to the DUT and compares the output with the result obtained by the high-level design. While Catapult is capable of translating assertions and coverage of properties for verification, it does not support covergroups and coverpoints. To address this, a script was developed to insert covergroups, coverpoints, and some assertions into the generated UVMF based on a configuration file. It can also apply several constraints to the random values generated by the testbench, or directly read the inputs from a specified file. Finally, it translates the same covergroups into C++. This allows verification engineers to quickly perform meaningful simulations for both high-level and RTL designs.