Design, analysis, and verification of a generic and optimum upsampler by 2 for a Wi-Fi 7 ASIC IP

The project is developed within the framework of a multi-rate digital signal processing (DSP) system, more specifically, within one of MaxLinear's Low-Power Wi-Fi 7 ASIC IPs. The work is centered in the development of a generic upsampler by 2 in SystemVerilog. The design not only meets the specifications for the upsamplers present in the transmission data path of the Wi-Fi IP but it also has extra features for future requirements, with the aim of reusing it with minimal or no changes. Digital design techniques are studied and implemented in order to optimize the design in terms of power consumption and area. In the development of the mentioned block, the design goes through many steps of the ASIC design flow, like RTL design description, functional verification and preliminary synthesis to obtain early area and power reports. In all these steps many commercial EDA tools were studied and a flow for accurate power estimation is proposed and implemented.