Architectural exploration of Logic-in-Memory systems with DExIMA-CAD

In the past years, the “memory wall problem” has questioned the feasibility of the traditional von Neumann architecture for new electronic systems. Due to several technological concerns, a performance bottleneck is found in the memory sub-system. As regards power consumption, energy is wasted in the processor-memory data traffic. The scientific literature is rich in examples of beyond von Neumann alternatives. For instance, in Logic-in-Memory (LiM) arrays, memory cells are endowed with computational capabilities, creating a naturally-parallel processing element. Thus, such structures may support SIMD operations and may successfully accelerate a large variety of algorithms. At the VLSI laboratory of the Politecnico di Torino, researchers have been studying LiM solutions, proving their effectiveness in mitigating the memory wall problem. The research work highlighted the need of new software tools to support the design flow for LiM architectures and to characterise their main figures of merit. Thus, a LiM development toolchain was born, which includes DExIMA (Design Explorer for In-Memory Architectures), a C++ performance, power and area estimator, and its Python front-end, DExIMA-CAD. The front-end provides an environment for the structural description of LiM systems, offering synthesis and estimation features. The aim of this thesis is to increase the architectural exploration capabilities of DExIMA-CAD and to integrate additional functionalities to support the LiM design flow. The revisited DExIMA-CAD is more versatile and efficient in the description of increasingly complex LiM systems, reducing the design time by a great amount. Furthermore, the new front-end features enlarge the set of algorithms that may be implemented by DExIMA-CAD. The support for intra-array interconnections is introduced, allowing the designer to integrate connections between the elements of a LiM array, thus boosting its processing abilities. A graph representation is employed to ease interconnections-related analysis and synthesis tasks. Furthermore, graphs provide specific tools to support a broader architectural-level exploration of the complete LiM system. As a consequence, in the uppermost level of the system, the designer may now allocate an arbitrary number of LiM arrays, instances of basic building blocks (e.g. flip-flops, logic gates, arithmetic circuits, registers and so forth) and, if required, more complex sub-systems. The increased breadth of the architectural exploration requires a versatile UVM testbench, which is automatically configured by DExIMA-CAD. A simulation dashboard helps the designer specify the algorithms implemented by each LiM array and the behaviour of the complete LiM system. Thus, the design and the simulation phases may take place completely within the toolchain environment. The revisited DExIMA-CAD is eventually employed to implement existing LiM architectures, including the components of an in-memory Binarized Neural Network and a general-purpose LiM co-processor (Hybrid-SIMD). In addition, the new front-end features are used to explore several in- memory solutions for the Advanced Encryption Standard (AES) algorithm. These case studies prove the effectiveness of DExIMA-CAD in supporting the LiM design flow for a large variety of architectures and algorithms.