One of the main issues that companies have to face is the presence of legacy systems: tools, methodologies, and processes that are not updated over time and that can become a relevant bottleneck in company production. The issue of legacy systems is present in the context of Apple’s Design-For-Test team. Specifically, during the Design Verification (DV) phase, where the design of a chip is verified through software simulations, the engineers have to manually check that the behavior of some specific signals is the one expected. This step is time-consuming, repetitive, and error-prone. In this Master Thesis, the process of developing an automation tool able to verify the behavior of a chip's signals during the Design Verification is presented.