The progress of semiconductor electronics devices has been marked by rapid improvement in terms of performance since the first MOSFET was invented in 1960. In the last decades the down-scaling of the transistor has led to increasing performance in electronic systems while following the Moore’s Law. However, this trend reached its limit, when the performance degradation of junction based metal-oxide-semiconductor field-effect-transistor (MOSFET) increased due to channel scaling. The limitations of the device related to the rising short channel effects (SCEs) are the threshold voltage (VTH) roll off, subthreshold current and drain-induced-barrier-lowering (DIBL). Moreover, process challenges concerning the fabrication of ultra steep p-n junctions restricts its functionality in the fabrication of the transistor itself.