AEQUAM, a fast and efficient quantum emulation toolchain

In recent decades, researchers are taking an increasing interest in defining new quantum algorithms, following a prospect of computational speedup. However, their functional verification is still challenging and expensive since real quantum hardware is costly and limited in terms of qubit count and noise, and software simulators suffer from very long execution times. This thesis presents AEQUAM, an Area Efficient QUAntum eMulator, to provide a faster and more accessible toolchain for the functional verification of algorithms defined according to the quantum circuit model. The emulator is a Field-Programmable-Gate-Array (FPGA)-based digital architecture, specialized in executing the operations needed to evaluate the ideal behavior of a given circuit. It uses a Single-Instruction-Multiple-Data (SIMD) approach with Reduced-Instruction-Set-Computer (RISC)-like instructions and exploits the sparse nature of the quantum gates unitary matrices to reduce the computational complexity of the overall emulation process. The AEQUAM architecture to be synthesized on a target FPGA is the result of a software toolchain responsible for generating a flexible hardware description. For instance, the user can select the desired number of emulated qubits and the degree of parallelization for the execution of a single gate. By exploring the space of solutions, it is possible to use the minimum area to emulate a fixed number of qubits, or vice versa to obtain the maximum qubit count from a set area constraint. This novel emulation approach supports quantum gates from the Clifford+T set and rotational gates, for example Rx, Ry and Rz. These last gates require trigonometric functions, for which a preliminary study of trade-offs between flexibility, accuracy, area, latency, and instruction width was done. Area is expected to exponentially increase when scaling the qubit count. For this purpose, a C++ model of the architecture helps evaluating the best numerical representation, parallelism, and rounding method. The model results are functionally compared with the Qiskit State Vector simulator, extracting figures of merit, like fidelity. These preliminary analyses suggest a 20-bit fixed point representation and a nearest-type approximation as viable design configuration. The AEQUAM toolchain consists of a system of Python scripts , employed both for compilation purposes, translating quantum circuits described in OPENQASM2.0 in executable instructions, and for automatically generating a part of the Register-Transfer-Level design, described in VHDL, according to the user’s choice regarding qubit count and degree of parallelization. Synthesis on an Altera Cyclone 10LP device attains six emulated qubits. While this result is close to the current literature, it is achieved with an FPGA smaller by several orders of magnitude. This ultimately suggests that the proposed architecture can deliver an even more significant qubit count on larger FPGAs. The architecture is tested on a VirtLAB board, developed in the VLSI Lab of Politecnico di Torino, that mounts an STM32L496 micro-controller and the target FPGA. The first one acts as bridge between the user PC and the emulator, providing the executable instructions to the FPGA and delivering the result to the PC at the end of the emulation procedure. The result of this thesis is the development of a toolchain for a fast and accurate quantum circuit emulation, that could be employed in the future for validating new quantum algorithms.