High-Level Design of 2D-Convolution Accelerators for AI Leveraging Embedded Scalable Platform (ESP)

Today, Artificial Intelligence (AI) is everywhere and it has made many technological applications more efficient and reliable. Convolutional Neural Networks (CNNs) are at the foundation of the vast majority of AI applications. This type of networks can be extremely accurate, but precision comes at a high computational cost due to the many mutliply-and-accumulate operations between feature and weight tensors that need to be performed. Loosely-coupled hardware accelerators supported by general-purpose processors are an effective way to speed up the computation of CNNs. Thus, the goal of this thesis is to design an accelerator that performs a specific type of convolution known as 2D convolution. The design process leverages High-Level Synthesis (HLS) and the Embedded Scalable Platform (ESP) tool, which simplifies accelerators design and their integration into heterogeneous System-On-Chip (SoC). This manuscript describes how neural networks work, paying particular attention to CNNs. The most successful ConvNet models for image classification are also taken into consideration and their architectures and performances are quickly compared. It continues showing how hardware accelerators can be used to perform specific functions that can be executed in parallel with other operations performed by the processor core. It also discusses on how accelerators can be easily designed and synthesized leveraging high-level synthesis tools, such as Catapult HLS. Then, it illustrates the open source ESP platform developed at Columbia University. ESP combines a flexible design methodology with a scalable architecture. This platform accommodates various Computer-Aided Design (CAD) tools and design flows. In addition, it facilitates the integration of different hardware blocks in an SoC which otherwise would be a very challenging and longer task. After this preliminary introduction, the thesis addresses the design of the 2Dconvolution accelerator. Each accelerator is integrated into an SoC which is prototyped on a proFPGA XC7V2000T FPGA with a single external DDR3 memory module. Different implementations of the same accelerator are proposed. The first implementation is a standard 2D convolution with a 18x18x32 input feature map tensor and a 7x7x32x32 weight tensor and it allows to get a latency of xxx ms and an area of xxx mm^2. For this architecture, the data reading phase, the convolution operation and the data write back phase are performed in a sequential way. The second implementation exploits HLS directives to perform these three different phases in a pipelined way using a hierarchical design. This results in a latency reduction of ”xxx%” at the cost of an area increase of ”xxx%” with respect to the standard approach. The third implementation uses line buffers to further reduce the memory accesses to the external memory, obtaining a final latency reduction of xxx ms with xxx mm^2 of area overhead. Finally, we added a second external DDR3 memory module to the proFPGA and we implemented a fourth version of the convolution algorithm that exploits the two external memories to access feature maps and weights in parallel. The results show a reduced latency of xxx % with xxx resource usage compared to the third implementation. This thesis contributes also to expand the documentation about the Catapult design flow of ESP with a 2D-convolution accelerator and explains how to configure ESP to support a proFPGA DDR3 S0-DIMM Adapter Board as second external memory instead of the ESP default one.