Wireless power and data transmission is an efficient method to develop miniaturised and highly distributed neural interfaces. Amplitude Shift Keying (ASK) modulation is commonly used in the case of ultra-miniaturised implants. Over the years, several ASK-based Clock Data Recovery (CDR) architectures have been proposed with different objectives, such as: increasing the data rate, decreasing the silicon area and reducing the power consumption. The state-of-the-art includes: synchronous architectures mainly relied on complex Phase Locked Loop (PLL) based circuits or asynchronous systems with the need of on-chip oscillators. This master’s thesis is a part of an ambitious project focused on reverting blindness, carried out in the Bio/CMOS Interfaces Group at Integrated Circuits Laboratory (EPFL, Neuchatel).