Ultralow latency audio processing via FPGA for Networked Music Performance applications

Among all computer architectures, Application-Specific Instruction set Processors (ASIP) are one of the solutions that can better host a custom application. Together with the usage of Field-Programmable Gate Array (FPGA) chips, they provide the best tradeoff regarding flexibility and performance, allowing for an efficient design chain. Transport Triggered Architectures (TTAs) are ASIP-like solutions that can offer quite exceptional features. The possibility of creating custom functional units to accelerate specific tasks and the opportunity of having program instructions that can host several move operations simultaneously lead to a highly optimized and parallel architecture. Furthermore, the possibility of programming TTA cores through a high-level language like C, using custom hardware operations, offers an additional level of freedom to the design, allowing an efficient codesign environment for present and future use cases. This thesis proposes an implementation for an FPGA TTA processor architecture integrated into a Networked Music Performance (NMP) application, an environment where musicians can play together remotely in real-time: custom hardware reduces the typical latencies given by processing, recording, and streaming of audio data. Results show that the implemented processor can easily record, stream and exchange audio data with the other devices composing the NMP environment, with enough space to add more processing power, eventually. Latency contributions introduced by the architecture are very low since the core can run at a clock speed of 100 MHz with optimized paths, potentially leading to an improvement with respect to software-based solutions.